Integrated circuit (IC) components are typically tested prior to use in a system. Such tests seek to verify proper functionality within each input/output (I/O) buffer of the integrated circuit component (e.g., processor, main memory device). The need for testing extends, likewise, to the system or platform of which the IC component is a part.
It is very costly to implement a logic design and subsequently detect errors in that design. It would be beneficial to detect errors in the logic design and effect design changes prior to implementation of the design (i.e., prior to silicon fabrication).
Typical pre-silicon validation of the logic design has two phases, the logic-level simulation and the analog simulation. The logic-level simulation is usually a 2-stage or 4-stage discrete simulation, which employs a number of AND gates, flops, etc., with binary results. The analog simulation, which models capacitors, resistors, gates, etc., is not binary, but provides a measurable slope. The problem with typical pre-silicon analog simulation is that it is limited in scope.
One type of analog simulation is AC I/O loopback simulation, which may be accomplished, post-silicon, using built-in self-test (BIST) circuitry implemented within each IC component, to verify, at speed, inter-component communications in the system. For example, an AC I/O loopback test may be effected by driving test data out of the IC component through an output portion of an I/O buffer. The data is then driven back through an input portion of the I/O buffer. The actual received (or driven) test values are then compared with corresponding expected values to verify proper functionality and timing of the input and output portion of each I/O buffer associated with each pin of the IC component. This allows a self-test of the I/O circuitry that is independent of the core logic of the IC component.
In a typical such system, the I/O buffer includes an I/O pad, an output driver, an input receiver, and a test circuit that generates test pattern signals when the I/O buffer is operating in a test mode. A latch is used to store an error signal that is generated as part of the test. The latch may be a boundary scan latch, the contents of which may be examined by other IC components of the system, or by an external testing apparatus, as part of a boundary scan-chain where test values from multiple IC components are shifted out serially. Using such a technique, test pattern values may be loaded into the latch one bit at a time, through a serial scan-in port, and read out of the latch serially through a scan-out port.
Such BIST circuitry may be implemented within various types of IC components including the processor, buffers, memory controller hub, I/O hub, etc., and may allow for testing of interconnects (e.g., buses) between components including the interface between boards.
The AC I/O loopback simulation is quite complex and provides a great deal of details regarding the IC component. This complexity is also the source of a disadvantage in that, due to its complexity, AC I/O loopback simulation can only be effected on a limited scope. The simulation can be effected for only a portion of the processor chip (e.g., several gates, a small circuit) at a time. That is, although it offers such benefits as accurate timing, RC effects, and slope information, prior art dynamic circuit simulation is limited by device count. Trying to include too many circuits in a dynamic simulation would increase simulation time to an unmanageable scale. So, though each component piece of the logic can be addressed, the combination, spanning the entire processor chip, is immense and contains too many pieces of logic (e.g., gates) to be accurately addressed by analog circuit simulation. Moreover, some portions of the system design, for systems of typical complexity, cannot be validated through analog circuit simulation due to the scope of the system.